Monolithic three‐dimensional integration of aligned carbon nanotube transistors for high‐performance integrated circuits

Carbon nanotube field-effect transistors (CNT FETs) have been demonstrated to exhibit high performance only through low-temperature fabrication process and require a low thermal budget construct monolithic three-dimensional (M3D) integrated circuits (ICs), which considered promising technology meet the demands of high-bandwidth computing fully functional integration. However, lack high-quality CNT materials at upper layer low-parasitic interlayer dielectric (ILD) makes reported M3D FETs ICs unable provide predicted performance. In this work, we demonstrate multilayer stackable for integration high-performance aligned carbon (A-CNT) ICs. A low-κ (~3) SiO2 is prepared from spin-on-glass (SOG) processes with highest temperature 220°C, presenting parasitic capacitance between two transistor layers excellent planarization offer an ideal surface A-CNT device process. film carrier mobility 650 cm2 V–1 s–1 on ILD clean transfer process, enabling fabricated on-state current (1 mA μm–1) peak transconductance (0.98 mS μm–1). The bottom maintain pristine after undergoing growth FET fabrication. As result, 5-stage ring oscillators utilizing architecture show gate propagation delay 17 ps active region approximately 100 μm2, representing fastest most compact date.